Basic Operation

To support Verilog designs, SIMetrix has a new device called VSXA. A VSXA device is defined by a .MODEL statement and this in turn specifies a Verilog design file. The Verilog file is expected to contain a top level module definition and this module defines the external connections to the analog system via Verilog ports.

Any number of Verilog devices (i.e. VSXA instances) can be placed in a SIMetrix netlist/schematic. The actual design presented to the Verilog simulator will be a single Verilog definition, but SIMetrix handles the task of creating this from the user's individual Verilog design files and schematic/netlist interconnection of VSXA instances.

See {Simulator Reference Manual/Analog Device Reference/Verilog-HDL Interface (VSXA)}{simref:AnalogDeviceReference:Verilog-HDLInterface(VSXA)} for more details about the VSXA device.