Test Details | |
Schematic | DVM -- PFC_CCM_sync_DLL.sxsch |
Test | LL_Nominal|F_Low|Disabled|100% Load|FindACSteadyState |
Date / Time | 22/03/2022 06:40 |
Report Directory | DVM_REPORTS\2022-03-22-06_18\LL_Nominal\F_Low\Disabled\100% Load\FindACSteadyState |
Log File | report.txt |
Screenshot | schematic.png |
Status | PASS |
Simulator | simplis |
Deck | input.deck |
Init | input.deck.init |
Measured Scalar Values | |
Frequency(SRC) | 50 |
ILOAD | MIN 248.6188m MAX 251.51182m |
ISRC | MIN -1.2397833 MAX 1.2397833 |
VLOAD | MIN 397.79008 MAX 402.41891 |
VLOAD %_diff_last_2_linecycles | 0.0000034680223% |
VLOAD At Simulation Start Time | AVG 400.09257 |
VLOAD Last LineCycle | AVG 400.093 |
VLOAD Previous LineCycle | AVG 400.093 |
VSRC | MIN -169.99978 MAX 169.99978 RMS 120.208 |
Measured Spec Values | |
AC_Settling(LOAD) | PASS: Voltage across LOAD has settled to (34.6802n) % and is less than or equal to Max Settling Spec of (10m) % |
Max_VLOAD | PASS: Max. Output1 Voltage (402.419) is less than or equal to Max. Output1 Voltage Spec (420) |
![]() LOAD
VLOAD
ILOAD
|
|
SXGPH File | simplis_tran61_4123.sxgph |
![]() SRC
VSRC
ISRC
|
|
SXGPH File | simplis_tran61_4112.sxgph |
Other SXGPH Files | |
Output#tran | simplis_tran61_3995.sxgph |
Vdc-Vdrain#tran | simplis_tran61_4006.sxgph |
SIGNAL#tran | simplis_tran61_4022.sxgph |
Samples#tran | simplis_tran61_4033.sxgph |
COMP#tran | simplis_tran61_4054.sxgph |
triggers#tran | simplis_tran61_4065.sxgph |
VL#tran | simplis_tran61_4101.sxgph |
Load_offset#tran | simplis_tran61_4160.sxgph |