back to overview ▲

» DVM Test Report: Efficiency and Loop Characterization|Vin Nominal|70% Load

Test Details
Schematic 8.2_LLC Closed Loop.sxsch
Test Efficiency and Loop Characterization|Vin Nominal|70% Load
Date / Time 12/10/2015 6:09 PM
Report Directory measure_loop_param\Efficiencyand Loop Characterization\Vin Nominal\70% Load
Log File report.txt
Screenshot schematic.png
Status PASS
Simulator simplis
Deck input.deck
Init input.deck.init
Measured Scalar Values
Efficiency 95.5828%
eta_nom 95.5828%
Frequency(CLK) 86.2238k
gain_crossover_freq 4.9051k
gain_margin 20.1294
gmargin_nom 20.1294
gxover_nom 4.9051k
ILOAD
AVG
3.51428
MIN
3.50917
MAX
3.51742
RMS
3.51429
PK2PK
8.24998m
iload_nom 3.51428
ISRC
AVG
233.183m
MIN
-536.304m
MAX
907.075m
RMS
455.32m
PK2PK
1.44338
min_phase 42.0352
min_phase_freq 4.9051k
phase_crossover_freq 19.5696k
phase_margin 41.6959
pmargin_nom 41.6959
Power(LOAD) 84.6758
Power(SRC) 88.5889
sw_freq_nom 86.2238k
VLOAD
AVG
24.0947
MIN
24.0598
MAX
24.1161
RMS
24.0947
PK2PK
56.3203m
VSRC
AVG
379.977
MIN
379.909
MAX
380.054
RMS
379.977
PK2PK
144.338m
Measured Spec Values
Max_VLOAD PASS: Max. Output1 Voltage (24.1161) is less than or equal to Max. Output1 Voltage Spec (25.2)
Min_VLOAD PASS: Min. Output1 Voltage (24.0598) is greater than or equal to Min. Output1 Voltage Spec (22.8)
min_gain_margin PASS: Gain Margin (20.1294) is greater than Min. Gain Margin (12)
min_phase_margin PASS: Phase Margin (41.6959) is greater than Min. Phase Margin (35)
Bode Plot
GAIN
PHASE
SXGPH File simplis_ac11_654.sxgph
LOAD
VLOAD
ILOAD
SXGPH File simplis_pop11_620.sxgph
SRC
VSRC
ISRC
SXGPH File simplis_pop11_610.sxgph
Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
SXGPH File simplis_pop11_601.sxgph
Secondary
CLK
ICout
Is1
Is2
Vs
SXGPH File simplis_pop11_615.sxgph
Other SXGPH Files
default#643#pop simplis_pop11_643.sxgph
Modulator#pop simplis_pop11_648.sxgph