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» DVM Test Report: Efficiency and Loop Characterization|Vin Nominal|10% Load

Test Details
Schematic 8.2_LLC Closed Loop.sxsch
Test Efficiency and Loop Characterization|Vin Nominal|10% Load
Date / Time 12/10/2015 6:07 PM
Report Directory measure_loop_param\Efficiencyand Loop Characterization\Vin Nominal\10% Load
Log File report.txt
Screenshot schematic.png
Status PASS
Simulator simplis
Deck input.deck
Init input.deck.init
Measured Scalar Values
Efficiency 95.2384%
eta_nom 95.2384%
Frequency(CLK) 89.0521k
gain_crossover_freq 1.71205k
gain_margin 29.2597
gmargin_nom 29.2597
gxover_nom 1.71205k
ILOAD
AVG
502.5m
MIN
502.391m
MAX
502.631m
RMS
502.5m
PK2PK
239.797u
iload_nom 502.5m
ISRC
AVG
33.4734m
MIN
-524.683m
MAX
523.85m
RMS
241.074m
PK2PK
1.04853
min_phase 109.687
min_phase_freq 1.71205k
phase_crossover_freq 38.4305k
phase_margin 109.61
pmargin_nom 109.61
Power(LOAD) 12.1087
Power(SRC) 12.7141
sw_freq_nom 89.0521k
VLOAD
AVG
24.097
MIN
24.0919
MAX
24.103
RMS
24.097
PK2PK
11.126m
VSRC
AVG
379.997
MIN
379.948
MAX
380.052
RMS
379.997
PK2PK
104.853m
Measured Spec Values
Max_VLOAD PASS: Max. Output1 Voltage (24.103) is less than or equal to Max. Output1 Voltage Spec (25.2)
Min_VLOAD PASS: Min. Output1 Voltage (24.0919) is greater than or equal to Min. Output1 Voltage Spec (22.8)
min_gain_margin PASS: Gain Margin (29.2597) is greater than Min. Gain Margin (12)
min_phase_margin PASS: Phase Margin (109.61) is greater than Min. Phase Margin (35)
Bode Plot
GAIN
PHASE
SXGPH File simplis_ac2_114.sxgph
LOAD
VLOAD
ILOAD
SXGPH File simplis_pop2_80.sxgph
SRC
VSRC
ISRC
SXGPH File simplis_pop2_70.sxgph
Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
SXGPH File simplis_pop2_61.sxgph
Secondary
CLK
ICout
Is1
Is2
Vs
SXGPH File simplis_pop2_75.sxgph
Other SXGPH Files
default#103#pop simplis_pop2_103.sxgph
Modulator#pop simplis_pop2_108.sxgph