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» DVM Test Report: Efficiency and Loop Characterization|Vin Minimum|100% Load

Test Details
Schematic 8.2_LLC Closed Loop.sxsch
Test Efficiency and Loop Characterization|Vin Minimum|100% Load
Date / Time 12/10/2015 6:16 PM
Report Directory measure_loop_param\Efficiencyand Loop Characterization\Vin Minimum\100% Load
Log File report.txt
Screenshot schematic.png
Status PASS
Simulator simplis
Deck input.deck
Init input.deck.init
Measured Scalar Values
Efficiency 95.0469%
eta_min 95.0469%
Frequency(CLK) 78.3325k
gain_crossover_freq 4.35094k
gain_margin 16.1516
gmargin_min 16.1516
gxover_min 4.35094k
ILOAD
AVG
5.00691
MIN
4.99645
MAX
5.01452
RMS
5.00691
PK2PK
18.0642m
iload_min 5.00691
ISRC
AVG
351.747m
MIN
-545.305m
MAX
1.25078
RMS
611.04m
PK2PK
1.79608
min_phase 53.4346
min_phase_freq 4.35094k
phase_crossover_freq 13.4603k
phase_margin 52.9692
pmargin_min 52.9692
Power(LOAD) 120.322
Power(SRC) 126.592
sw_freq_min 78.3325k
VLOAD
AVG
24.0311
MIN
23.981
MAX
24.0675
RMS
24.0311
PK2PK
86.5049m
VSRC
AVG
359.965
MIN
359.875
MAX
360.055
RMS
359.965
PK2PK
179.608m
Measured Spec Values
Max_VLOAD PASS: Max. Output1 Voltage (24.0675) is less than or equal to Max. Output1 Voltage Spec (25.2)
Min_VLOAD PASS: Min. Output1 Voltage (23.981) is greater than or equal to Min. Output1 Voltage Spec (22.8)
min_gain_margin PASS: Gain Margin (16.1516) is greater than Min. Gain Margin (12)
min_phase_margin PASS: Phase Margin (52.9692) is greater than Min. Phase Margin (35)
Bode Plot
GAIN
PHASE
SXGPH File simplis_ac42_2514.sxgph
LOAD
VLOAD
ILOAD
SXGPH File simplis_pop42_2480.sxgph
SRC
VSRC
ISRC
SXGPH File simplis_pop42_2470.sxgph
Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
SXGPH File simplis_pop42_2461.sxgph
Secondary
CLK
ICout
Is1
Is2
Vs
SXGPH File simplis_pop42_2475.sxgph
Other SXGPH Files
default#2503#pop simplis_pop42_2503.sxgph
Modulator#pop simplis_pop42_2508.sxgph